Seiichi Sato, Shido Onishi, Ritsuko Eguchi, Takahisa Ichinohe
ECS Meet. Abstr. MA2026-01(31) 1479 2026年7月7日 筆頭著者責任著者
Chaos-based secure communication provides a hardware-oriented approach to security by leveraging the extreme sensitivity and unpredictability of nonlinear dynamical systems. When the parameters of a chaotic oscillator are coupled to a physical device exhibiting state- and rate-dependent resistance, the resulting dynamics become increasingly difficult to model or replicate numerically. Among candidate devices, memristors display nonlinear, state- and rate-dependent resistance with current–voltage (I–V) hysteresis pinched at—and crossing—the origin, reflecting true resistive-memory behavior. In contrast, SiO 2 nanofilms—fully CMOS-compatible and fabrication-stable—exhibit quasi-memristive resistive dynamics: their I–V loops resemble those of memristors but do not cross the origin, indicating the absence of genuine resistive memory [1,2]. Unlike a memristor, which maintains its resistance state when the voltage crosses the I–V origin, an SiO 2 nanofilm reverts to its high-resistance state. In systems with frequently alternating input voltages, SiO 2 nanofilms undergo resistance changes more often than true memristors, producing richer perturbations to the chaotic trajectory. These contrasting device behaviors raise the question: how do a standard memristive model and a memory-free SiO 2 quasi-memristive model perform as physical keys in chaos-based secure communication?
Hardware implementation of chaos introduces additional considerations. In analog chaotic communication, channel noise from imperfect transmission readily disrupts synchronization. Conversely, purely digital implementations eliminate subtle analog fluctuations—such as thermal noise—that can enhance the unpredictability of chaotic dynamics through sensitivity to initial conditions. Hybrid architectures, combining digitally generated chaotic dynamics with analog physical keys, offer a balance between communication robustness and physically induced deviations that continuously perturb the chaotic trajectory in unpredictable ways.
In this work, we use system-level simulations to compare two physical-key models—an HP-type TiO 2 memristor and a quasi-memristive SiO 2 nanofilm—within hybrid chaos-based encryption systems. We first verify reliable decryption with each device and then evaluate their encryption performance.
To evaluate synchronization and encryption performance, the hybrid chaos-based communication system was implemented in MATLAB/Simulink. The core chaotic dynamics were realized in discrete time, while the physical key was modeled as an analog nonlinear device. Two key models were examined: an HP-type memristor representing TiO 2 devices [3], and a quasi-memristive SiO 2 nanofilm derived from our experimental characterization [2].
Figure 1 illustrates a hybrid communication system incorporating an SiO 2 nanofilm as the analog physical key. A digitally implemented Lorenz chaotic oscillator generates the carrier waveform, which is modulated by the input data (Fig. 1A) and transmitted to the receiver (Fig. 1B). Two receivers are considered: one using a resistor approximately matching the SiO 2 nanofilm’s resistance, and one employing the SiO 2 nanofilm model. Each time-domain waveform in Fig. 1A–D shows a short excerpt of the data stream. The right-hand panels display the corresponding I–V characteristics of the key elements. The resistor exhibits a linear response, whereas the SiO 2 nanofilm produces a broad, dynamically varying quasi-memristive loop whose width and shape evolve with the broadband spectral components of the chaotic waveform. These resistance fluctuations continuously deflect the chaotic trajectory, making synchronization more difficult for a mismatched receiver. As a result, the resistor-based receiver fails to recover the meaningful data (Fig. 1C), while the SiO 2 -keyed receiver achieves complete decoding with 100% bit matching (Fig. 1D).
When the SiO 2 nanofilm is replaced with an HP-type TiO 2 memristor model, the matched receiver also achieves 100% bit matching, demonstrating that both devices can serve as effective keys within the hybrid architecture. To evaluate encryption performance, we analyzed information entropy, adjacent-pixel correlation, the χ 2 test of histogram uniformity, the number of pixel change rate (NPCR), and the unified average changing intensity (UACI). Even without a physical key, the Lorenz-based chaotic system already exhibits high performance in these metrics. Integrating the HP-type memristor produced negligible changes, confirming that its inclusion does not degrade cryptographic performance. Incorporating the SiO 2 nanofilm preserved this high performance while slightly increasing information entropy toward the ideal randomness value and reducing the χ 2 statistic, indicating enhanced resistance to histogram-based statistical attacks. These results provide a unified view of how true and quasi-memristive behaviors influence chaos-based hardware security and clarify the distinct roles each device can play in physical-key cryptographic systems.
[1] T. Suzuki, K. Ando, T. Ichinohe, S. Sato, ECS Meet. Abstr . MA2024-02 , 4650 (2024).
[2] S. Sato, K. Ando, T. Suzuki, R. Eguchi, T. Ichinohe, Jpn. J. Appl. Phys . 64 , 10SP02 (2025).
[3] A. G. Alharbi, M. H. Chowdhury, Memristor Emulator Circuits (Springer, 2020).
Figure 1
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